Using Hardware Description Language (HDL), a digital design can be first described at an abstract level (i.e. Register Transfer Level—RTL or above) in terms of its functionality and data flow. The functionality of the digital design is validated before the digital design is fabricated on a chip. A logic synthesis tool then converts the RTL description to a gate-level netlist, which is a description of the digital design in terms of gates and connections among them. An automatic place and route tool subsequently creates a physical layout based on the gate-level netlist. The physical layout for the digital design is finally fabricated on a chip.
There exist two approaches to validating digital designs, namely, a simulation approach and a formal verification approach. Simulation is traditionally the main tool to perform a digital design validation. Specifically, a simulation tool receives an executable description of a digital design and a sequence of test stimuli, and then executes the description using the sequence of stimuli as inputs. The simulation tool validates the correctness of the design by comparing the simulated outputs with the desired outputs. However, as the complexity of a digital design increases, it is difficult to write a set of test stimuli sequences that would simulate all aspects of a digital design. Due to the limitations of a selected sequence of test stimuli, a simulation process may only cover some aspects of all possible functionality scenarios. This is known as the coverage problem. To improve coverage, a great effort has been made in manually improving test stimuli for validating different aspects of a digital design. Because a designer who is writing test stimuli sequences may not be able to fully anticipate complex scenarios in a design, a substantial portion of simulation time can be wasted in repetitively validating the same or similar functionality scenarios, leaving some other scenarios un-validated. In addition, manually writing a set of test stimuli sequences is a tedious and time-consuming task.
Unlike simulation, formal verification, a relatively newer approach, does not need a set of test stimuli to perform digital design validations. Instead, formal verification enumerates all possible test stimuli, in accordance with a stimulus specification, to validate a digital design. Thus, formal verification offers complete coverage for digital design validations. However, formal verification requires much larger memory space than simulation. Typically, even for a digital design with moderate complexity, formal verification may require more than 10 GB (Giga Byte) of memory space. Hence, formal verification is not feasible to validate complex digital designs due to memory limitations in existing formal verification tools.
Furthermore, most previous digital designs have been validated on simulation infrastructure. During many years of practice, the circuit design industry has accumulated extensive expertise (or intellectual property, such as a database of test stimuli) in, and made huge investment in, simulation infrastructure. Because of these expertise and investment, it is not feasible for the industry to totally abandon existing simulation infrastructure and build formal verification infrastructure from scratch.
There is, therefore, a need for a method and apparatus to validate digital designs with improved validation coverage and simulation efficiency.
There is another need for a method and apparatus to validate digital designs with improved validation coverage without requiring an excessive memory space.
There is yet another need for a method and apparatus to validate digital designs with improved validation coverage using a set of stimuli that may be not complete and well designed.
There is still another need for a method and apparatus to utilize welldeveloped existing simulation tools and infrastructures to validate increasingly complex digital designs with improved coverage and reduced simulation time.
The present invention provides a method and apparatus to meet these needs.